89 search results - page 5 / 18 » An Architecture for Combined Test Data Compression and Abort... |
DAC
2003
ACM
13 years 11 months ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
DATE
2008
IEEE
14 years 7 days ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
DAC
2003
ACM
13 years 11 months ago
2003
ACM
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
DATE
2008
IEEE
14 years 7 days ago
2008
IEEE
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
EGPGV
2004
Springer
13 years 11 months ago
2004
Springer
We describe a system for the texture-based direct volume visualization of large data sets on a PC cluster equipped with GPUs. The data is partitioned into volume bricks in object ...