10 search results - page 2 / 2 » An Effective Cache Overlapping Storage Structure for SMT Pro... |
IEEEPACT
2006
IEEE
13 years 11 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
SIGMETRICS
2011
ACM
12 years 7 months ago
2011
ACM
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
CGO
2004
IEEE
13 years 8 months ago
2004
IEEE
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
EUROSYS
2011
ACM
12 years 8 months ago
2011
ACM
Buffer caches in operating systems keep active file blocks in memory to reduce disk accesses. Related studies have been focused on how to minimize buffer misses and the caused pe...
ISPASS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper, we introduce PTLsim, a cycle accurate full system x86-64 microprocessor simulator and virtual machine. PTLsim models a modern superscalar out of order x86-64 proces...