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JISE
2011
58views more  JISE 2011»
13 years 8 days ago
An Efficient Architecture for a TCP Offload Engine Based on Hardware/Software Co-design
Hankook Jang, Sang-Hwa Chung, Dong Kyue Kim, Yun-S...
CCECE
2006
IEEE
13 years 11 months ago
A Hardware/Software Co-Design for RSVP-TE MPLS
This paper presents a hardware/software co-design for Multi Protocol Label Switching (MPLS) using RSVP-TE as a signaling protocol. MPLS is the protocol framework on which the atte...
Raymond Peterkin, Dan Ionescu
ERSA
2006
133views Hardware» more  ERSA 2006»
13 years 6 months ago
An FPGA based Co-Design Architecture for MIMO Lattice Decoders
MIMO systems have attracted great attentions because of their huge capacity. The hardware implementation of MIMO decoder becomes a challenging task as the complexity of the MIMO sy...
Cao Liang, Jing Ma, Xin-Ming Huang
CODES
1996
IEEE
13 years 9 months ago
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
The TaSCA environment for hardware/software co-design of control dominated systems implemented on a single chip includes a novel approach to the system exploration phase for the e...
Alessandro Balboni, William Fornaciari, Donatella ...
ISPASS
2010
IEEE
14 years 5 days ago
Hardware prediction of OS run-length for fine-grained resource customization
—In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors...
David Nellans, Kshitij Sudan, Rajeev Balasubramoni...