10 search results - page 2 / 2 » An Efficient Fault-Tolerant Routing Methodology for Meshes a... |
SAC
2005
ACM
13 years 11 months ago
2005
ACM
This paper presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. Our system requires an extremely high level of ro...
DSD
2006
IEEE
13 years 11 months ago
2006
IEEE
Region concept helps to accommodate cores larger than the tile size in mesh topology NoC architectures. In addition, it offers many new opportunities for NoC design, as well as pr...
DSD
2006
IEEE
13 years 9 months ago
2006
IEEE
Abstract-- Networks-on-Chip will serve as the central integration platform in future complex SoC designs, composed of a large number of heterogeneous processing resources. Most res...
HPCA
2003
IEEE
14 years 5 months ago
2003
IEEE
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unreali...