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EUROPAR
2001
Springer
14 years 3 months ago
VIA Communication Performance on a Gigabit Ethernet Cluster
As the technology for high-speed networks has evolved over the last decade, the interconnection of commodity computers (e.g., PCs and workstations) at gigabit rates has become a re...
Mark Baker, Paul A. Farrell, Hong Ong, Stephen L. ...
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
14 years 5 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
DAC
2007
ACM
14 years 11 months ago
Fast Second-Order Statistical Static Timing Analysis Using Parameter Dimension Reduction
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
Zhuo Feng, Peng Li, Yaping Zhan
ISCAS
2007
IEEE
180views Hardware» more  ISCAS 2007»
14 years 5 months ago
Characterization of a Fault-tolerant NoC Router
— With increasing reliability concerns for current and next generation VLSI technologies, fault-tolerance is fast becoming an integral part of system-on-chip (SoC) and multicore ...
Sumit D. Mediratta, Jeffrey T. Draper
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
14 years 11 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...