55 search results - page 1 / 11 » An Efficient Hybrid Cache Coherence Protocol for Shared Memo... |
ICPP
1996
IEEE
13 years 9 months ago
1996
IEEE
ISCA
1993
IEEE
13 years 9 months ago
1993
IEEE
Advances in circuit and integration technology are continuously boosting the speed of microprocessors. One of the main challenges presented by such developments is the effective u...
ISCA
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper introduces dynamic self-invalidation (DSI), a new technique for reducing cache coherence overhead in shared-memory multiprocessors. DSI eliminates invalidation messages...
DSD
2006
IEEE
13 years 8 months ago
2006
IEEE
Title of thesis: Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering Alokika Dash, Master of Science, 2006 Thesis dire...
HIPC
2007
Springer
13 years 11 months ago
2007
Springer
Traditional directory-based cache coherence protocols suffer from long-latency cache misses as a consequence of the indirection introduced by the home node, which must be accessed...