113 search results - page 1 / 23 » An Efficient Two-Level Partitioning Algorithm for VLSI Circu... |
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
In this paper, we present a fast and efficient Iterative Improvement Partitioning (IIP) technique for VLSI circuits and hybrid bucket structures on its implementation. Due to thei...
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
In this paper, we study the area-balanced multi-way partitioning problem of VLSI circuits based on a new dual netlist representation named the hybrid dual netlist (HDN), and propo...
EAAI
2006
13 years 5 months ago
2006
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI ...
ASYNC
2001
IEEE
13 years 9 months ago
2001
IEEE
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...