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ICMCS
2005
IEEE
133views Multimedia» more  ICMCS 2005»
13 years 11 months ago
Architecture for area-efficient 2-D transform in H.264/AVC
As the VLSI technology advances continuously, ASIC can easily achieve the required performance and most of them are actually over-designed. Thus, architecture shrinking is inevita...
Yu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei ...
ISCAS
2003
IEEE
93views Hardware» more  ISCAS 2003»
13 years 10 months ago
A rescheduling and fast pipeline VLSI architecture for lifting-based discrete wavelet transform
In this paper, we propose a fast pipeline VLSI architecture for 1D lifting-based discrete wavelet transform (DWT). This design method merges the filtering steps called the predict...
Bing-Fei Wu, Chung-Fu Lin
TCSV
2002
103views more  TCSV 2002»
13 years 5 months ago
A scalable and programmable architecture for 2-D DWT decoding
The compression of still images by means of the discrete wavelet transform (DWT), adopted in the JPEG-2000 and MPEG-4 standards, is becoming more and more widespread because it yie...
Massimo Ravasi, L. Tenze, Marco Mattavelli