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» An Embedded IDDQ Testing Architecture and Technique
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ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 3 months ago
Characterizing within-die variation from multiple supply port IDDQ measurements
-- The importance of within-die process variation and its impact on product yield has increased significantly with scaling. Within-die variation is typically monitored by embedding...
Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic
SERA
2005
Springer
13 years 11 months ago
A Design and Test Technique for Embedded Software
In recent years, embedded systems have become so complex and the development time to market is required to be shorter than before. As embedded systems include more functions for n...
Byeongdo Kang, Young-Jik Kwon, Roger Y. Lee
DFT
2004
IEEE
101views VLSI» more  DFT 2004»
13 years 9 months ago
Designs for Reducing Test Time of Distributed Small Embedded SRAMs
This paper proposes a test architecture aimed at reducing test time of distributed small embedded SRAMs (eSRAMs). This architecture improves the one proposed in [4, 5]. The improv...
Baosheng Wang, Yuejian Wu, André Ivanov
BIRTHDAY
2012
Springer
12 years 1 months ago
The Logical Execution Time Paradigm
Embedded systems must interact with their real-time environment in a timely and dependable fashion. Most embeddedsystems architectures and design processes consider “nonfunction...
Christoph M. Kirsch, Ana Sokolova
MTDT
2002
IEEE
108views Hardware» more  MTDT 2002»
13 years 10 months ago
A Fault Modeling Technique to Test Memory BIST Algorithms
The amount of memory being embedded on chip is growing rapidly. This strongly implies that memory Built-in-self-test (BIST) logic assumes utmost importance amongst all on chip sel...
Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil ...