51 search results - page 1 / 11 » An Evaluation of Memory Consistency Models for Shared-Memory... |
ASPLOS
1996
ACM
13 years 10 months ago
1996
ACM
ISCA
1997
IEEE
13 years 10 months ago
1997
IEEE
Current microprocessors aggressively exploit instructionlevel parallelism (ILP) through techniques such as multiple issue, dynamic scheduling, and non-blocking reads. Recent work ...
ISCA
1993
IEEE
13 years 10 months ago
1993
IEEE
We evaluate the e ect of processor speed, network bandwidth, and software overhead on the performance of release-consistent software distributed shared memory. We examine ve di er...
HPCA
1999
IEEE
13 years 10 months ago
1999
IEEE
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
ASPLOS
1991
ACM
13 years 9 months ago
1991
ACM
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...