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CAMP
2000
IEEE
13 years 9 months ago
An FPGA Architecture for High Speed Edge and Corner Detection
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per sec...
Cesar Torres-Huitzil, Miguel Arias-Estrada
CCECE
2006
IEEE
13 years 11 months ago
Hardware Edge Detection using an Altera Stratix NIOS2 Development Kit
— Edge detection is a computer vision algorithm that is very processor intensive. It is possible to increase the speed of the algorithm by using hardware parallelism. This paper ...
Jay Kraut
ICC
2007
IEEE
137views Communications» more  ICC 2007»
13 years 11 months ago
A Novel Algorithm and Architecture for High Speed Pattern Matching in Resource-Limited Silicon Solution
— Network Intrusion Detection Systems (NIDS) are more and more important for identifying and preventing the malicious attacks over the network. This paper proposes a novel cost-e...
Nen-Fu Huang, Yen-Ming Chu, Chi-Hung Tsai, Chen-Yi...
INFOCOM
2006
IEEE
13 years 11 months ago
Reverse Hashing for High-Speed Network Monitoring: Algorithms, Evaluation, and Applications
— A key function for network traffic monitoring and analysis is the ability to perform aggregate queries over multiple data streams. Change detection is an important primitive w...
Robert T. Schweller, Zhichun Li, Yan Chen, Yan Gao...
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 9 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus