27 search results - page 2 / 6 » An Improved Algorithm for Minimum-Area Retiming |
DAC
2003
ACM
14 years 6 months ago
2003
ACM
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock ...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
Nested loops are the most critical sections in many scientific and Digital Signal Processing (DSP) applications. It is important to study effective and efficient transformation ...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
State elements are increasingly vulnerable to soft errors due to their decreasing size, and the fact that latched errors cannot be completely eliminated by electrical or timing ma...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...