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DFT
2005
IEEE
63views VLSI» more  DFT 2005»
13 years 10 months ago
An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors
Paolo Bernardi, Leticia Maria Veiras Bolzani, Maur...
DSN
2005
IEEE
13 years 10 months ago
On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core
1 In sub-micron technology circuits high integration levels coupled with the increased sensitivity to soft errors even at ground level make the task of guaranteeing systems’ depe...
Paolo Bernardi, Leticia Maria Veiras Bolzani, Maur...
TDSC
2010
111views more  TDSC 2010»
13 years 3 months ago
Using Underutilized CPU Resources to Enhance Its Reliability
—Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft ...
Avi Timor, Avi Mendelson, Yitzhak Birk, Neeraj Sur...
ICCD
2007
IEEE
152views Hardware» more  ICCD 2007»
13 years 8 months ago
Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors
As application-specific instruction set processors (ASIPs) are being increasingly used in mobile embedded systems, the ubiquitous networking connections have exposed these systems...
Hai Lin, Xuan Guan, Yunsi Fei, Zhijie Jerry Shi
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
13 years 10 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni