8 search results - page 2 / 2 » An O(mn) time algorithm for optimal buffer insertion of nets... |
ASPDAC
2005
ACM
13 years 7 months ago
2005
ACM
Abstract— As technology scales to 0.13 micron and below, designs are requiring buffers to be inserted on interconnects of even moderate length for both critical paths and fixing...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
In high-speed digital VLSI design, bounding the load capacitance at gate outputs is a well-known methodology to improve coupling noise immunity, reduce degradation of signal trans...
ISQED
2005
IEEE
13 years 11 months ago
2005
IEEE
Hierarchical approach greatly facilitates large-scale chip design by hiding distracting details in low-level objects. However, the lowlevel designs have to have a global view of h...