Sciweavers

79 search results - page 15 / 16
» An adjoint method for second-order switching time optimizati...
Sort
View
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 2 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
TSP
2008
118views more  TSP 2008»
13 years 6 months ago
Channel-Aware Random Access Control for Distributed Estimation in Sensor Networks
A cross-layered slotted ALOHA protocol is proposed and analyzed for distributed estimation in sensor networks. Suppose that the sensors in the network record local measurements of ...
Y.-W. P. Hong, Keng-U Lei, Chong-Yung Chi
LCTRTS
2010
Springer
14 years 26 days ago
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture
A large number of embedded systems include 8-bit microcontrollers for their energy efficiency and low cost. Multi-bank memory architecture is commonly applied in 8-bit microcontr...
Minming Li, Chun Jason Xue, Tiantian Liu, Yingchao...
BIOINFORMATICS
2005
152views more  BIOINFORMATICS 2005»
13 years 6 months ago
Intervention in context-sensitive probabilistic Boolean networks
Motivation: Intervention in a gene regulatory network is used to help it avoid undesirable states, such as those associated with a disease. Several types of intervention have been...
Ranadip Pal, Aniruddha Datta, Michael L. Bittner, ...
IPPS
2003
IEEE
13 years 11 months ago
Parallel ROLAP Data Cube Construction On Shared-Nothing Multiprocessors
The pre-computation of data cubes is critical to improving the response time of On-Line Analytical Processing (OLAP) systems and can be instrumental in accelerating data mining tas...
Ying Chen, Frank K. H. A. Dehne, Todd Eavis, Andre...