High-level synthesis challenges and solutions for a dynamically reconfigurable processor

A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone finite state machine and that switches “contexts” consisting of many operational and storage units in processing elements (PEs) and wires between them. Utilizing the resources not only in two spatial dimensions but also vertically (time-multiplexed) under accurate timing and area constraints imposes challenges for a high-level synthesizer for the DRP. We describe a C-based behavioral synthesis method which features data path generation with clock speed optimization. This is achieved by including the overhead of selectors in the scheduling algorithm, and considering a wire delay at each PE level. A new technique is introduced to achieve high area efficiency. It works by effectively allocating multiple steps into the context. From the original highlevel synthesizer for application-specific integrated circu...

• Type: Conference
• Year: 2006
• Where: ICCAD
• Authors: Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, Toru Awashima, Kazutoshi Wakabayashi, Li Jing
• Keywords: DRP Architecture, Generated Data Paths, Hardware, ICCAD 2006, Reconfigurable Data Paths