28 search results - page 5 / 6 » An analytic placer for mixed-size placement and timing-drive... |
ICCAD
2002
IEEE
13 years 10 months ago
2002
IEEE
IP blocks and large macro cells are increasingly prevalent in physical design, actually causing an increase in the available free space for the dust logic. We observe that top-dow...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
Many current integrated circuits designs, such as those released for the ISPD2005[14] placement contest, are extremely large and can contain a great deal of white space. These new...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits. FlowPlace includes: a) a t...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
This work focuses on congestion-driven placement of standard cells into rows in the fixed-die context. We summarize the stateof-the-art after two decades of research in recursive ...
ASPDAC
2000
ACM
13 years 10 months ago
2000
ACM
Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs 10, 16 . Placement quality is evaluated in terms of the half-perimeter wirelen...