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DAC
2000
ACM

179views Computer Architecture» more DAC 2000»

An architecture-driven metric for simultaneous placement and global routing for FPGAs

14 years 5 months ago

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FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...

Yao-Wen Chang, Yu-Tsang Chang

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Id	Views	Title	Status

1	179	An architecture-driven metric for simultaneous placement and global routing for FPGAs	claim
2	179	Dynamic power management of complex systems using generalized stochastic Petri nets	claim
3	175	Block placement with symmetry constraints based on the O-tree non-slicing representation	claim
4	165	Code compression for low power embedded system design	claim
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6	151	Hardware implementation of communication protocols modeled by concurrent EFSMs with multi-way synchronization	claim
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8	148	CYCLONE: automated design and layout of RF LC-oscillators	claim
9	146	MorphoSys: case study of a reconfigurable computing system targeting multimedia applications	claim
10	143	The design and use of simplepower: a cycle-accurate energy estimation tool	claim
11	141	Compiling Esterel into sequential code	claim
12	141	Impact of interconnect variations on the clock skew of a gigahertz microprocessor	claim
13	140	Run-time voltage hopping for low-power real-time systems	claim
14	139	COSY communication IP's	claim
15	139	Forensic engineering techniques for VLSI CAD tools	claim
16	139	Passive model order reduction of multiport distributed interconnects	claim
17	134	Test challenges for deep sub-micron technologies	claim
18	131	Can recursive bisection alone produce routable placements?	claim
19	131	An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects	claim
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21	129	System design of active basestations based on dynamically reconfigurable hardware	claim
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23	128	Dynamic noise analysis in precharge-evaluate circuits	claim
24	127	Embedded hardware and software self-testing methodologies for processor cores	claim
25	125	Hardware-software co-design of embedded reconfigurable architectures	claim
26	124	Watermarking while preserving the critical path	claim
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29	120	A multi-interval Chebyshev collocation method for efficient high-accuracy RF circuit simulation	claim
30	119	Unifying behavioral synthesis and physical design	claim
31	118	Improved fault diagnosis in scan-based BIST via superposition	claim
32	118	Large-scale capacitance calculation	claim
33	116	Critical path analysis using a dynamically bounded delay model	claim
34	116	Efficient methods for embedded system design space exploration	claim
35	115	Designing systems-on-chip using cores	claim
36	115	Projection frameworks for model reduction of weakly nonlinear systems	claim
37	114	Depth optimal incremental mapping for field programmable gate arrays	claim
38	114	High-level simulation of substrate noise generation including power supply noise coupling	claim
39	113	Analysis of composition complexity and how to obtain smaller canonical graphs	claim
40	113	Convex delay models for transistor sizing	claim
41	113	Symbolic timing simulation using cluster scheduling	claim
42	113	Boolean satisfiability in electronic design automation	claim
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44	112	Memory aware compilation through accurate timing extraction	claim
45	111	GTX: the MARCO GSRC technology extrapolation system	claim
46	111	Model-based dummy feature placement for oxide chemical-mechanical polishing manufacturability	claim
47	110	Power minimization using control generated clocks	claim
48	107	Interactive co-design of high throughput embedded multimedia	claim
49	107	System chip test: how will it impact your design?	claim
50	106	Verification of configurable processor cores	claim
51	106	Hierarchical analysis of power distribution networks	claim
52	106	TACO: timing analysis with coupling	claim
53	106	Using general-purpose programming languages for FPGA design	claim
54	105	Formal verification of iterative algorithms in microprocessors	claim
55	104	Wave-steering one-hot encoded FSMs	claim
56	104	Fingerprinting intellectual property using constraint-addition	claim
57	104	Optimizing sequential verification by retiming transformations	claim
58	103	High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system	claim
59	103	Macro-driven circuit design methodology for high-performance datapaths	claim
60	103	BDS: a BDD-based logic optimization system	claim
61	102	Bus encoding for low-power high-performance memory systems	claim
62	102	Practical iterated fill synthesis for CMP uniformity	claim
63	102	Power analysis of embedded operating systems	claim
64	102	Influence of compiler optimizations on system power	claim
65	102	YAPI: application modeling for signal processing systems	claim
66	102	Efficient variable ordering using aBDD based sampling	claim
67	102	Multiple Si layer ICs: motivation, performance analysis, and design implications	claim
68	101	Removing user specified false paths from timing graphs	claim
69	100	Performance analysis and optimization of latency insensitive systems	claim
70	98	Fast methods for extraction and sparsification of substrate coupling	claim
71	98	To split or to conjoin: the question in image computation	claim
72	97	Predicting performance potential of modern DSPs	claim
73	96	Synthesis and optimization of coordination controllers for distributed embedded systems	claim
74	96	Task generation and compile-time scheduling for mixed data-control embedded software	claim
75	96	Efficient building block based RTL code generation from synchronous data flow graphs	claim
76	94	Efficient error detection, localization, and correction for FPGA-based debugging	claim
77	94	Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter	claim
78	94	Function-level power estimation methodology for microprocessors	claim
79	94	Static noise analysis for digital integrated circuits in partially-depleted silicon-on-insulator technology	claim
80	94	Singularity-treated quadrature-evaluated method of moments solver for 3-D capacitance extraction	claim
81	93	On switch factor based analysis of coupled RC interconnects	claim
82	93	MINFLOTRANSIT: min-cost flow based transistor sizing tool	claim
83	90	Interconnect testing in cluster-based FPGA architectures	claim
84	89	Performance driven multi-level and multiway partitioning with retiming	claim
85	84	Timing-driven placement based on partitioning with dynamic cut-net control	claim
86	83	Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques	claim
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88	83	Reliable verification using symbolic simulation with scalar values	claim
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90	78	Power minimization derived from architectural-usage of VLIW processors	claim
91	78	Maze routing with buffer insertion and wiresizing	claim
92	76	Synthesis of application-specific memories for power optimization in embedded systems	claim
93	75	The use of carry-save representation in joint module selection and retiming	claim

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