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» An architectural exploration of via patterned gate arrays
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TC
2008
13 years 11 months ago
Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations
This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In ...
Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. V...
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 8 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
DAC
2007
ACM
15 years 2 days ago
Trusted Hardware: Can It Be Trustworthy?
Processing and storage of confidential or critical information is an every day occurrence in computing systems. The trustworthiness of computing devices has become an important co...
Cynthia E. Irvine, Karl N. Levitt
ICES
2001
Springer
107views Hardware» more  ICES 2001»
14 years 3 months ago
Polymorphic Electronics
This paper introduces the concept of polymorphic electronics (polytronics) –referring to electronics with superimposed built-in functionality. A function change does not require ...
Adrian Stoica, Ricardo Salem Zebulum, Didier Keyme...
VLSID
2001
IEEE
164views VLSI» more  VLSID 2001»
14 years 11 months ago
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers
In this paper, we propose a new transparent built-in self-test ( TBIST ) method to test multiple embedded memory arrays with various sizes in parallel. First, a new transparent tes...
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das