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» An area-optimality study of floorplanning
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MICRO
2006
IEEE
144views Hardware» more  MICRO 2006»
13 years 11 months ago
Die Stacking (3D) Microarchitecture
3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die ...
Bryan Black, Murali Annavaram, Ned Brekelbaum, Joh...
MJ
2011
288views Multimedia» more  MJ 2011»
13 years 8 days ago
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
New tendencies envisage 2D/3D Multi-Processor System-On-Chip (MPSoC) as a promising solution for the consumer electronics market. MPSoCs are complex to design, as they must execute...
Pablo Garcia Del Valle, David Atienza
ISPD
1997
ACM
110views Hardware» more  ISPD 1997»
13 years 9 months ago
Performance driven global routing for standard cell design
Advances in fabrication technology have resulted in a continual shrinkage of device dimensions. This has resulted in smaller device delays, greater resistance along interconnect w...
Jason Cong, Patrick H. Madden
BMCBI
2008
137views more  BMCBI 2008»
13 years 5 months ago
VennMaster: Area-proportional Euler diagrams for functional GO analysis of microarrays
Background: Microarray experiments generate vast amounts of data. The functional context of differentially expressed genes can be assessed by querying the Gene Ontology (GO) datab...
Hans A. Kestler, André Müller, Johann ...