23 search results - page 5 / 5 » An asynchronous fpga logic cell implementation |
ARCS
2006
Springer
13 years 9 months ago
2006
Springer
: Given is the following "creature's exploration problem": n creatures are moving around in an unknown environment in order to visit all cells in shortest time. This...
ICCD
2002
IEEE
14 years 2 months ago
2002
IEEE
In this paper, a parallel Variable-Length Decoding (VLD) scheme is introduced. The scheme is capable of decoding all the codewords in an N-bit buffer whose accumulated codelength ...
FCCM
2002
IEEE
13 years 10 months ago
2002
IEEE
The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing re...