MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64

The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing resource and its associated instructions, with respect to an entropy decoding task which is to be executed on the FPGA-augmented TriMedia/CPU64 processor. We first outline the extension of the TriMedia/CPU64 architecture, which consists of an FPGA–based Reconfigurable Functional Unit (RFU) and the associated generic instructions. Then we address entropy decoding and propose a strategy to partially break the data dependency related to variable-length decoding. Three VLDs (VLD-1, VLD-2, VLD-3) instructions which can return 1, 2, or 3 symbols, respectively, are subsequently analyzed. After completing the DSE, we determined that VLD-2 instruction leads to the most efficient entropy decoding in terms of instruction cycles and FPGA area. The FPGA–based implementation of the computing resource associated to VLD...

• Type: Conference
• Year: 2002
• Where: FCCM
• Authors: Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers
• Keywords: Efficient Entropy Decoding, Entropy Decoding, Entropy Decoding Task, FCCM 2002, VLSI