178 search results - page 2 / 36 » An efficient approach for error diagnosis in HDL design |
DAC
1998
ACM
14 years 6 months ago
1998
ACM
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
ISMVL
2007
IEEE
13 years 11 months ago
2007
IEEE
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such syst...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
—Functional simulation is still the primary workhorse for verifying the functional correctness of hardware designs. Functional verification is necessarily incomplete because it i...
VTS
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process...
CSREAESA
2008
13 years 6 months ago
2008
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...