26 search results - page 2 / 6 » An efficient transistor optimizer for custom circuits |
ISQED
2010
IEEE
13 years 11 months ago
2010
IEEE
With the CMOS transistors being scaled to sub 45nm and lower, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging pr...
CSREAESA
2004
13 years 6 months ago
2004
To perform digital logic in CMOS in a truly adiabatic (asymptotically thermodynamically reversible) fashion requires that logic transitions be driven by a quasitrapezoidal (flat-t...
ICCAD
1997
IEEE
13 years 9 months ago
1997
IEEE
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ii) library mapping phase. Typically, the structures and the sizes of the gates in ...
ARITH
2007
IEEE
13 years 9 months ago
2007
IEEE
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determi...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as hig...