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ISQED   2010 International Symposium on Quality Electronic Design
Wall of Fame | Most Viewed ISQED-2010 Paper
ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
10 years 5 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
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