176 search results - page 2 / 36 » An error simulation based approach to measure error coverage... |
DAC
2001
ACM
14 years 6 months ago
2001
ACM
roperty Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines Dong Wang , Pei-Hsin Ho , Jiang Long , James Kukula Yunshan Zhu , Tony Ma , Robert D...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
We describe a technique for verifying that a hardware design correctly implements a protocol-level formal specification. Simulation steps are translated to protocol state transiti...
DAC
1997
ACM
13 years 9 months ago
1997
ACM
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper describes an efficient error simulator able to analyze functional VHDL descriptions. The proposed simulation environment can be based on commercial VHDL simulators. Al...
WSC
2007
13 years 7 months ago
2007
Generation of traces from a simulation model and their analysis is a powerful and common mean to debug simulation models. In this paper, we define a measure of progress for simul...