139 search results - page 1 / 28 » An evolutionary algorithm for reducing integrated-circuit te... |
SAC
2002
ACM
13 years 4 months ago
2002
ACM
The cost for testing integrated circuits represents a growing percentage of the total cost for their production. The former strictly depends on the length of the test session, and...
EVOW
2001
Springer
13 years 9 months ago
2001
Springer
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective faul...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The tradeoffs between per...
DAC
2003
ACM
13 years 10 months ago
2003
ACM
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architect...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper we propose a new compression algorithm geared to reduce the time needed to test scan-based designs. Our scheme compresses the test vector set by encoding the bits th...