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» An evolutionary approach to timing driven FPGA placement
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ICCAD
2004
IEEE
155views Hardware» more  ICCAD 2004»
14 years 2 months ago
A flexibility aware budgeting for hierarchical flow timing closure
—In this paper, we present a new block budgeting algorithm which speeds up timing closure in timing driven hierarchical flows. After a brief description of the addressed flow, ...
Olivier Omedes, Michel Robert, Mohammed Ramdani
IPPS
2009
IEEE
14 years 4 days ago
Exploring FPGAs for accelerating the phylogenetic likelihood function
Driven by novel biological wet lab techniques such as pyrosequencing there has been an unprecedented molecular data explosion over the last 2-3 years. The growth of biological seq...
Nikolaos Alachiotis, Euripides Sotiriades, Apostol...
FPL
2003
Springer
113views Hardware» more  FPL 2003»
13 years 10 months ago
Data Dependent Circuit Design: A Case Study
Abstract. Data dependent circuits are logic circuits specialized to specific input data. They are smaller and faster than the original circuits, although they are not reusable and...
Shoji Yamamoto, Shuichi Ichikawa, Hiroshi Yamamoto
ISPD
2005
ACM
205views Hardware» more  ISPD 2005»
13 years 11 months ago
Coupling aware timing optimization and antenna avoidance in layer assignment
The sustained progress of VLSI technology has altered the landscape of routing which is a major physical design stage. For timing driven routings, traditional approaches which con...
Di Wu, Jiang Hu, Rabi N. Mahapatra
GECCO
2007
Springer
183views Optimization» more  GECCO 2007»
13 years 11 months ago
Screening the parameters affecting heuristic performance
This research screens the tuning parameters of a combinatorial optimization heuristic. Specifically, it presents a Design of Experiments (DOE) approach that uses a Fractional Fac...
Enda Ridge, Daniel Kudenko