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    ICCAD
    1997
    IEEE
    75views Hardware» more  ICCAD 1997»
    An exact gate decomposition algorithm for low-power technology mapping
    13 years 9 months ago
    An exact gate decomposition algorithm for low-power technology mapping
    Download  www.cecs.uci.edu
    With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In...
    Hai Zhou, D. F. Wong
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    DAC
    1996
    ACM
    125views Computer Architecture» more  DAC 1996»
    Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
    13 years 9 months ago
    Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design
    Download  cadlab.cs.ucla.edu
    In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...
    Jason Cong, Yean-Yow Hwang
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    FPGA
    2001
    ACM
    145views FPGA» more  FPGA 2001»
    Simultaneous logic decomposition with technology mapping in FPGA designs
    13 years 10 months ago
    Simultaneous logic decomposition with technology mapping in FPGA designs
    Download  cadlab.cs.ucla.edu
    Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
    Gang Chen, Jason Cong
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    FPGA
    2007
    ACM
    185views FPGA» more  FPGA 2007»
    Power-aware FPGA logic synthesis using binary decision diagrams
    13 years 11 months ago
    Power-aware FPGA logic synthesis using binary decision diagrams
    Download  www.ecs.umass.edu
    Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
    Kevin Oo Tinmaung, David Howland, Russell Tessier
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    ICCAD
    1995
    IEEE
    134views Hardware» more  ICCAD 1995»
    A delay model for logic synthesis of continuously-sized networks
    13 years 9 months ago
    A delay model for logic synthesis of continuously-sized networks
    Download  www.cs.york.ac.uk
    ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
    Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
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