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ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 14 days ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
FPGA
2006
ACM
155views FPGA» more  FPGA 2006»
13 years 8 months ago
Improvements to technology mapping for LUT-based FPGAs
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
DAC
2008
ACM
14 years 5 months ago
SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models
SystemCoDesigner is an ESL tool developed at the University of Erlangen-Nuremberg, Germany. SystemCoDesigner offers a fast design space exploration and rapid prototyping of behavi...
Christian Haubelt, Thomas Schlichter, Joachim Kein...
ICCAD
2001
IEEE
201views Hardware» more  ICCAD 2001»
14 years 1 months ago
An Integrated Data Path Optimization for Low Power Based on Network Flow Method
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
Chun-Gi Lyuh, Taewhan Kim, Chien-Liang Liu
ISSS
1999
IEEE
151views Hardware» more  ISSS 1999»
13 years 9 months ago
Optimized System Synthesis of Complex RT Level Building Blocks from Multirate Dataflow Graphs
In order to cope with the ever increasing complexity of todays application specific integrated circuits, a building block based design methodology is established. The system is co...
Jens Horstmannshoff, Heinrich Meyr