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» An on Chip ADC Test Structure
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ADC
2006
Springer
158views Database» more  ADC 2006»
13 years 11 months ago
Dimensionality reduction in patch-signature based protein structure matching
Searching bio-chemical structures is becoming an important application domain of information retrieval. This paper introduces a protein structure matching problem and formulates i...
Zi Huang, Xiaofang Zhou, Dawei Song, Peter Bruza
DAC
2000
ACM
14 years 6 months ago
Self-test methodology for at-speed test of crosstalk in chip interconnects
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
Xiaoliang Bai, Sujit Dey, Janusz Rajski
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
13 years 10 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ITC
1998
IEEE
71views Hardware» more  ITC 1998»
13 years 9 months ago
A structured and scalable mechanism for test access to embedded reusable cores
The main objective of core-based IC design is improvement of design efficiency and time-to-market. In order to prevent test development from becoming the bottleneck in the entire ...
Erik Jan Marinissen, Robert G. J. Arendsen, Gerard...
FMCAD
2007
Springer
13 years 11 months ago
Formal Verification of Partial Good Self-Test Fencing Structures
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...
Adrian E. Seigler, Gary A. Van Huben, Hari Mony