65 search results - page 3 / 13 » An on Chip ADC Test Structure |
GLOBECOM
2009
IEEE
13 years 10 months ago
2009
IEEE
Abstract--This paper presents several on-chip antenna structures that may be fabricated with standard CMOS technology for use at millimeter wave frequencies. On-chip antennas for w...
DATE
2008
IEEE
14 years 16 days ago
2008
IEEE
The importance of testing approaches that exploit error tolerance to improve yield has previously been established. Error rate, defined as the percentage of vectors for which the...
JSA
2000
13 years 5 months ago
2000
As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benef...
ETS
2011
IEEE
12 years 5 months ago
2011
IEEE
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
ISPD
2004
ACM
13 years 11 months ago
2004
ACM
This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the pow...