Sciweavers

7 search results - page 1 / 2
» Analog and Digital Circuit Design in 65 nm CMOS: End of the ...
Sort
View
DATE
2005
IEEE
133views Hardware» more  DATE 2005»
13 years 10 months ago
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?
Georges G. E. Gielen, Wim Dehaene, Phillip Christi...
DATE
2008
IEEE
144views Hardware» more  DATE 2008»
13 years 11 months ago
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces
The prospective use of upcoming nanometer CMOS technology nodes (65nm, 45nm, and beyond) in bioelectronic interfaces is raising a number of important issues concerning circuit arc...
Carlotta Guiducci, Alexandre Schmid, Frank K. G&uu...
ICCAD
2006
IEEE
208views Hardware» more  ICCAD 2006»
14 years 1 months ago
Automation in mixed-signal design: challenges and solutions in the wake of the nano era
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design comp...
Trent McConaghy, Georges G. E. Gielen
ISQED
2011
IEEE
240views Hardware» more  ISQED 2011»
12 years 7 months ago
Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling
—Design optimization methodologies for AMS-SoCs with analog, digital, and mixed-signal portions have not received significant attention, due to their high complexity. In mixed-s...
Oleg Garitselov, Saraju P. Mohanty, Elias Kougiano...
DAC
2008
ACM
14 years 5 months ago
The mixed signal optimum energy point: voltage and parallelism
An energy optimization is proposed that addresses the nontrivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and b...
Brian P. Ginsburg, Anantha P. Chandrakasan