10 search results - page 2 / 2 » Analysis of on-chip inductance effects for distributed RLC i... |
DAC
1999
ACM
14 years 6 months ago
1999
ACM
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
A closed form expression for the rise time of a gate driving a distributed RLC line is introduced that is within 8% of dynamic circuit simulations for a wide range of RLC loads. I...
INTEGRATION
2007
13 years 5 months ago
2007
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tap...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper focuses on statistical interconnect timing analysis in a parameterized block-based statistical static timing analysis tool. In particular, a new framework for performin...