20 search results - page 1 / 4 » Analysis of power-clocked CMOS with application to the desig... |
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
A significant fraction of the total power in highly synchronous systems is dissipated over clock networks. Hence, low-power clocking schemes would be promising approaches for futu...
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
⎯ This paper presents our research results on power-clocked CMOS design. First we provide algebraic expressions and describe properties of clocked signals. Next two types of powe...
ENGL
2007
13 years 4 months ago
2007
—A hybrid translinear (TL) circuit constituted by two kinds of transistors, bipolar and CMOS transistors, was proposed to control its quiescent current. And a new method was intr...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
—We present experimental results from an integrated circuit designed for wireless neural recording applications. The chip, which was fabricated in a 0.6-µm 2P3M BiCMOS process, ...
CDES
2006
13 years 6 months ago
2006
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...