Sciweavers

11 search results - page 3 / 3
» Analyzing Metric Space Indexes: What For
Sort
View
ISQED
2010
IEEE
141views Hardware» more  ISQED 2010»
14 years 3 days ago
Assessing chip-level impact of double patterning lithography
—Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32nm and 22nm process nodes, relative to costlier technology optio...
Kwangok Jeong, Andrew B. Kahng, Rasit Onur Topalog...