Abstract- This paper proposes a hardwadsoftware cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG correspondingto an application program and a timing ...
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...
This paper presents a methodology for monitoring security in Application Specific Instruction-set Processors (ASIPs). This is a generalized methodology for inline monitoring insec...
Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad ...
Analytical modeling is applied to the automated design of application-specific superscalar processors. Using an analytical method bridges the gap between the size of the design sp...
Abstract - Using the
exibility provided by multiple functionalities we have developed a new approach for permanent fault-tolerance: Heterogeneous BuiltIn-Resiliency (HBIR). HBIR p...