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ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
13 years 3 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
13 years 12 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
FPL
2009
Springer
107views Hardware» more  FPL 2009»
13 years 10 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...
SACRYPT
2001
Springer
106views Cryptology» more  SACRYPT 2001»
13 years 10 months ago
Fast Normal Basis Multiplication Using General Purpose Processors
—For cryptographic applications, normal bases have received considerable attention, especially for hardware implementation. In this article, we consider fast software algorithms ...
Arash Reyhani-Masoleh, M. Anwarul Hasan
EH
2004
IEEE
117views Hardware» more  EH 2004»
13 years 9 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...