We propose a provably efficient application-controlled global strategy for organizing a cache of size k shared among P application processes. Each application has access to informa...
Rakesh D. Barve, Edward F. Grove, Jeffrey Scott Vi...
Next generation computer systems will have gigabytes of physical memory and processors in the 200 MIPS range or higher. While this trend suggests that memory management for most p...
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multi...
As the last-level on-chip caches in chip-multiprocessors increase in size, the physical locality of on-chip data becomes important for delivering high performance. The non-uniform...