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GLVLSI
2010
IEEE
141views VLSI» more  GLVLSI 2010»
13 years 5 months ago
Energy-efficient redundant execution for chip multiprocessors
Relentless CMOS scaling coupled with lower design tolerances is making ICs increasingly susceptible to wear-out related permanent faults and transient faults, necessitating on-chi...
Pramod Subramanyan, Virendra Singh, Kewal K. Saluj...
LCTRTS
2010
Springer
13 years 3 months ago
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, program...
Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin,...
HPCA
2007
IEEE
14 years 6 months ago
Evaluating MapReduce for Multi-core and Multiprocessor Systems
This paper evaluates the suitability of the MapReduce model for multi-core and multi-processor systems. MapReduce was created by Google for application development on data-centers...
Colby Ranger, Ramanan Raghuraman, Arun Penmetsa, G...
DSN
2007
IEEE
13 years 12 months ago
Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor
Aggressive CMOS scaling will make future chip multiprocessors (CMPs) increasingly susceptible to transient faults, hard errors, manufacturing defects, and process variations. Exis...
Christopher LaFrieda, Engin Ipek, José F. M...
FGCS
2006
115views more  FGCS 2006»
13 years 5 months ago
A universal performance factor for multi-criteria evaluation of multistage interconnection networks
The choice of an interconnection network for a parallel computer depends on a large number of performance factors which are very often application dependent. We propose a performa...
Ahmad Chadi Aljundi, Jean-Luc Dekeyser, M. Tahar K...