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» Applying WCET Analysis at Architectural Level
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DAC
2004
ACM
14 years 6 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw
DAC
2003
ACM
14 years 6 months ago
A cost-driven lithographic correction methodology based on off-the-shelf sizing tools
As minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requir...
Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, J...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
13 years 11 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
DAC
2003
ACM
13 years 10 months ago
Determining appropriate precisions for signals in fixed-point IIR filters
This paper presents an analytical framework for the implementation of digital infinite impulse response filters in fixed-point hardware on field programmable gate arrays. This ana...
Joan Carletta, Robert J. Veillette, Frederick W. K...
DAC
2007
ACM
13 years 9 months ago
Statistical Framework for Technology-Model-Product Co-Design and Convergence
This paper presents a statistical framework to cooperatively design and develop technology, product circuit, benchmarking and model early in the development stage. The statistical...
Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Ol...