22 search results - page 3 / 5 » Architectural and compiler support for energy reduction in t... |
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
ISPDC
2010
IEEE
13 years 3 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
DAC
2002
ACM
14 years 6 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
—In this paper, an energy-efficient and high performance ternary content addressable memory (TCAM) are presented. It employs the concept of “green” microarchitecture and circ...
HIPC
1999
Springer
13 years 9 months ago
1999
Springer
We describe a radically new cache architecture and demonstrate that it offers a huge reduction in cache cost, size and power consumption whilst maintaining performance on a wide ra...