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» Architectural approaches to reduce leakage energy in caches
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MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
13 years 5 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
TC
2008
13 years 5 months ago
On-Demand Solution to Minimize I-Cache Leakage Energy with Maintaining Performance
This paper describes a new on-demand wake-up prediction policy for reducing leakage power. The key insight is that branch prediction can be used to selectively wake up only the nee...
Sung Woo Chung, Kevin Skadron
PACS
2000
Springer
121views Hardware» more  PACS 2000»
13 years 9 months ago
Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we ex...
Stefanos Kaxiras, Zhigang Hu, Girija J. Narlikar, ...
EUC
2004
Springer
13 years 11 months ago
Non-uniform Set-Associative Caches for Power-Aware Embedded Processors
Abstract. Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Especially, as the transistor supply voltag...
Seiichiro Fujii, Toshinori Sato
MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
13 years 10 months ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...