15 search results - page 1 / 3 » Architectural energy optimization by bus splitting |
TCAD
2002
13 years 4 months ago
2002
This paper proposes split shared-bus architecture to reduce the energy dissipation for global data exchange among a set of interconnected modules. The bus splitting problem for mi...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
– A split-bus architecture is proposed to improve the power dissipation for global data exchange among a set of modules. The resulting bus splitting problem is formulated and sol...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
With technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The Energyoptima...
DATE
2005
IEEE
13 years 6 months ago
2005
IEEE
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
SLIP
2006
ACM
13 years 10 months ago
2006
ACM
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...