110 search results - page 3 / 22 » Architectural simulation for a programmable DSP chip set |
IEEEPACT
2000
IEEE
13 years 10 months ago
2000
IEEE
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
The memory subsystem is a major contributor to the performance, power, and area of complex SoCs used in feature rich multimedia products. Hence, memory architecture of the embedded...
CODES
2007
IEEE
14 years 15 days ago
2007
IEEE
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
DAC
2000
ACM
14 years 7 months ago
2000
ACM
The effect of crosstalk errors is most significant in highperformance circuits, mandating at-speed testing for crosstalk defects. This paper describes a self-test methodology that...
DSD
2004
IEEE
13 years 10 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...