218 search results - page 2 / 44 » Architecture Level Power-Performance Tradeoffs for Pipelined... |
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
This paper presents a new methodology for system-level power and performance analysis of wireless multimedia systems. More precisely, we introduce an analytical approach based on ...
VLSID
2008
IEEE
14 years 5 months ago
2008
IEEE
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
FPGA
1999
ACM
13 years 9 months ago
1999
ACM
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
HPCA
1998
IEEE
13 years 9 months ago
1998
IEEE
The counterflow pipeline concept was originated by Sproull et al.[1] to demonstrate the concept of asynchronous circuits. This architecture relies on distributed decision making an...
FCCM
1998
IEEE
13 years 9 months ago
1998
IEEE
ended abstract defines a class of architectures for pipeline reconfigurable FPGAs by parameterizing a generic model. This class of architectures is sufficiently general to allow e...