75 search results - page 15 / 15 » Architecture and Hardware for Scheduling Gigabit Packet Stre... |
MEMOCODE
2010
IEEE
13 years 2 months ago
2010
IEEE
Abstract--This paper shows an implementation of CANSCID (Combined Architecture for Stream Categorization and Intrusion Detection). To satisfy the required system throughput, the pa...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
CCS
2008
ACM
13 years 6 months ago
2008
ACM
This paper examines a new building block for next-generation networks: SNAPP, or Stateless Network-Authenticated Path Pinning. SNAPP-enabled routers securely embed their routing d...
INFOCOM
2007
IEEE
13 years 11 months ago
2007
IEEE
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
RTAS
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper focuses on a technique to empower commercial-off-the-shelf (COTS) systems with an execution environment, and corresponding services, to support realtime and embedded ap...