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ICCAD
1998
IEEE
100views Hardware» more  ICCAD 1998»
13 years 9 months ago
Architecture driven circuit partitioning
Chau-Shen Chen, TingTing Hwang, C. L. Liu
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
13 years 9 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
VLSID
2003
IEEE
167views VLSI» more  VLSID 2003»
14 years 5 months ago
Timing Minimization by Statistical Timing hMetis-based Partitioning
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
Cristinel Ababei, Kia Bazargan
DAC
1996
ACM
13 years 9 months ago
Partitioning of VLSI Circuits and Systems
Partitioning plays an increasingly important role in the design process of VLSI circuits and systems. There are partitioning to be solved on all levels of abstraction. The rapidly...
Frank M. Johannes
CLEIEJ
2010
13 years 2 months ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...