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QOSA
2007
Springer
13 years 11 months ago
A Bayesian Model for Predicting Reliability of Software Systems at the Architectural Level
: Modern society relies heavily on complex software systems for everyday activities. Dependability of these systems thus has become a critical feature that determines which product...
Roshanak Roshandel, Nenad Medvidovic, Leana Golubc...
JSS
2002
131views more  JSS 2002»
13 years 5 months ago
Experiences with ALMA: Architecture-Level Modifiability Analysis
Modifiability is an important quality for software systems, because a large part of the costs associated with these systems is spent on modifications. The effort, and therefore co...
Nico H. Lassing, PerOlof Bengtsson, Hans van Vliet...
ISPASS
2008
IEEE
13 years 12 months ago
Metrics for Architecture-Level Lifetime Reliability Analysis
Abstract— This work concerns metrics for evaluating microarchitectural enhancements to improve processor lifetime reliability. A commonly reported reliability metric is mean time...
Pradeep Ramachandran, Sarita V. Adve, Pradip Bose,...
ICCD
2005
IEEE
159views Hardware» more  ICCD 2005»
13 years 11 months ago
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors
Nanoelectronic devices are expected to have extremely high and variable fault rates; thus future processor architectures based on these unreliable devices need to be built with fa...
Wenjing Rao, Alex Orailoglu, Ramesh Karri
VLSID
2003
IEEE
183views VLSI» more  VLSID 2003»
14 years 6 months ago
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks
We present an innovative design of an accurate, 2D DCT IDCT processor, which handles scaled and sub-sampled input blocks efficiently. In the IDCT mode, the latency of the processo...
Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van...