36 search results - page 3 / 8 » Architectures and Execution Models for Hardware Software Com... |
SIGPLAN
2008
13 years 5 months ago
2008
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
ISCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
DSD
2011
IEEE
12 years 5 months ago
2011
IEEE
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...